1. Field of the Invention
This invention relates in general to electronic devices and, more particularly, to improved means and methods for providing small high performance devices with sidewall contacts, suitable for use in large scale integrated circuits.
2. Background Art
There is an ongoing desire in the semiconductor art to produce transistors having smaller and smaller dimensions. This is because, in many applications, faster performance, lower power dissipation, and/or more complex circuits can be obtained with smaller devices. It is generally also desired that the individual devices be electrically isolated one from the other.
With high speed low power bipolar transistors and integrated circuits, for example, the individual devices are usually isolated by a combination of junction isolation and oxide filled trenches in the semiconductor substrate. Typically, metallic interconnects are made to emitter, base, and collector contact regions on the upper surface of the active portions of the device. Minimum device size is usually limited by the minimum lithographic dimensions, the need for providing alignment tolerance among the successive mask layers, and the need for providing contacts on the device surface.
While the available device structures and methods permit very complex integrated circuits to be fabricated, they still suffer from a number of significant limitations. For example, in a typical planar bipolar transistor the base-collector junction area and the collector-substrate junction area are larger than is necessary merely for the desired transistor action because of the need to provide room on the upper surface of the device for the contact regions. These larger than desired junction areas can introduce unwanted parasitic capacitance which limits the device or circuit performance. The larger areas can also limit the attainable packing density and circuit complexity.
A partial solution to this problem has been suggested in the prior art by use of "pillar" transistors employing lateral polycrystalline base contacts. However, these prior art structures still suffer from excessive collector-substrate capacitance and are not easily interconnected because they have a substrate collector contact. Thus, a need continues to exist for device structures and fabrication methods which overcome or avoid one or more limitations of the prior art.
Accordingly, it is an object of the present invention to provide improved means and methods for fabricating minimum geometry semiconductor devices which have reduced base-collector and collector-substrate junction areas.
It is an additional object of the present invention to provide improved means and methods for forming semiconductor devices in which electrical connections to the buried active device regions are made laterally.
It is a further object of the present invention to provide improved means and methods for forming bipolar transistors using buried sidewall contacts to base and collector regions.
It is additional object of the present invention to provide improved means and methods for providing device structures which can be individually isolated.
It is a further object of the present invention to provide improved means and methods for fabricating devices in which the device active areas, contacts, and isolation walls are self-aligned and whose dimensions and separations are controlled by a single masking layer.
It is an additional object of the present invention to provide improved means and methods for interconnecting devices and device regions using isolated buried conductor layers formed at the same time as the lateral device contacts.
As used herein, the words "polycrystalline" or "poly" are intended to include all non-single crystal forms of solids. As used herein, the words "dip etching" are intended to include all forms of blanket etching or erosion, and are not intended to be limited merely to wet chemical etching.